SH7261 Datasheet, PDF (925/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
Table 20.6 Functions of Each Block
Block
Internal bus interface
IEBus interface
Register
Transmit controller
Receive controller
Transmit data buffer
Receive data buffer
Function
Internal bus interface
• Data width: 8 bits
• IEB register access
Interface conforms to IEBus specifications
• Outputs data from transmit controller to IEBus in IEBus
specification bit format
• Picks out frame data in IEBus specification bit format to transfer
to receive controller
IEB control register
• Register to control IEB
• Readable/writable from internal bus
Transmits data in transmit buffer to IEBus
• Generates transmit frame combining header information in
register and data in transmit buffer to transmits
• Detects transmit error
Stores data from IEBus in receive buffer
• Stores header information and data in received frame in register
and receive buffer, respectively
• Detects receive error
Buffer for data transmission
• Buffer that stores data to be transmitted to IEBus
• Buffer size: 128 bytes
Buffer for data reception
• Buffer that stores data received from IEBus
• Buffer size: 128 bytes
Rev. 2.00 Sep. 07, 2007 Page 893 of 1312
REJ09B0320-0200