SH7261 Datasheet, PDF (159/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.3.4 Interrupt Control Register 2 (ICR2)
ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT7
to PINT0 individually: low level or high level. ICR2 is initialized by a power-on reset or in deep
standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
PINT PINT PINT PINT PINT PINT PINT PINT
7S 6S 5S 4S 3S 2S 1S 0S
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 8
Bit Name

7
PINT7S
6
PINT6S
5
PINT5S
4
PINT4S
3
PINT3S
2
PINT2S
1
PINT1S
0
PINT0S
[Legend]
n = 7 to 0
Initial
Value
All 0
0
0
0
0
0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value
should always be 0.
R/W PINT Sense Select
R/W These bits select whether interrupt signals
R/W ^{corresponding to pins PINT7 to PINT0 are detected by}
a low level or high level.
R/W _{0: Interrupt request is detected on low level of PINTn}
R/W input
R/W 1: Interrupt request is detected on high level of PINTn
R/W
input
R/W
6.3.5 IRQ Interrupt Request Register (IRQRR)
IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0.
If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after
reading IRQ7F to IRQ0F = 1 cancels the retained interrupts.
IRQRR is initialized by a power-on reset or in deep standby mode.
Rev. 2.00 Sep. 07, 2007 Page 127 of 1312
REJ09B0320-0200