SH7261 Datasheet, PDF (729/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.5 Bit Rates and SCBRR Settings (Clocked Synchronous Mode) (2)
Pφ (MHz)
Bit Rate 33
36
38
40
(bit/s)
n
N
n
N
n
N
n
N
110
—
—
—
—
—
—
—
—
250
—
—
—
—
—
—
—
—
500
3
255
—
—
—
—
—
—
1k
3
125
3
140
3
147
3
155
2.5 k
2
200
2
224
2
237
2
249
5k
2
100
2
112
2
118
2
124
10 k
1
200
1
224
1
237
1
249
25 k
1
80
1
89
1
94
1
99
50 k
0
160
0
179
0
189
0
199
100 k
0
80
0
89
0
94
0
99
250 k
0
31
0
35
0
37
0
39
500 k
0
15
0
17
0
18
0
19
1M
0
7
0
8
—
—
0
9
2M
—
—
—
—
—
—
—
—
[Legend]
Blank: No setting possible
—: Setting possible, but error occurs
*:
Continuous transmission/reception not possible
Table 16.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is
used. Tables 16.7 and 16.8 list the maximum rates when the external clock input is used.
Rev. 2.00 Sep. 07, 2007 Page 697 of 1312
REJ09B0320-0200