SH7261 Datasheet, PDF (13/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

7.3.4 Break Data Mask Register (BDMR)..................................................................... 171
7.3.5 Break Bus Cycle Register (BBR).......................................................................... 172
7.3.6 Break Control Register (BRCR) ........................................................................... 174
7.4 Operation ........................................................................................................................... 177
7.4.1 Flow of the User Break Operation ........................................................................ 177
7.4.2 Break on Instruction Fetch Cycle.......................................................................... 178
7.4.3 Break on Data Access Cycle................................................................................. 179
7.4.4 Value of Saved Program Counter ......................................................................... 180
7.4.5 Usage Examples.................................................................................................... 181
7.5 Usage Notes ....................................................................................................................... 184
Section 8 Cache .................................................................................................187
8.1 Features.............................................................................................................................. 187
8.1.1 Cache Structure..................................................................................................... 187
8.2 Register Descriptions ......................................................................................................... 190
8.2.1 Cache Control Register 1 (CCR1) ........................................................................ 190
8.2.2 Cache Control Register 2 (CCR2) ........................................................................ 192
8.3 Operation ........................................................................................................................... 195
8.3.1 Searching Cache ................................................................................................... 195
8.3.2 Read Access.......................................................................................................... 197
8.3.3 Prefetch Operation (Only for Operand Cache) ..................................................... 197
8.3.4 Write Operation (Only for Operand Cache).......................................................... 197
8.3.5 Write-Back Buffer (Only for Operand Cache)...................................................... 198
8.3.6 Coherency of Cache and External Memory .......................................................... 200
8.4 Memory-Mapped Cache .................................................................................................... 200
8.4.1 Address Array ....................................................................................................... 200
8.4.2 Data Array ............................................................................................................ 201
8.4.3 Usage Examples.................................................................................................... 203
8.4.4 Notes ..................................................................................................................... 204
Section 9 Bus State Controller (BSC)................................................................205
9.1 Features.............................................................................................................................. 205
9.2 Input/Output Pins ............................................................................................................... 207
9.3 Area Overview ................................................................................................................... 209
9.3.1 Address Map ......................................................................................................... 209
9.3.2 Data Bus Width and Pin Function Setting for Individual Areas ........................... 210
9.4 Register Descriptions ......................................................................................................... 211
9.4.1 CSn Control Register (CSnCNT) (n = 0 to 6)....................................................... 213
9.4.2 CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6) ............................. 215
9.4.3 SDRAMCm Control Register (SDCmCNT) (m = 0, 1)........................................ 217
Rev. 2.00 Sep. 07, 2007 Page xiii of xxxii