SH7261 Datasheet, PDF (359/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value
R/W Description
9
SRLOD
0
R/W DMA Source Address Reload Function Enable
This bit specifies whether or not the source address is
reloaded when the DMA transfer end condition is
detected.
When this bit is cleared to "0", reloading is not
executed.
When this bit is set to "1" and the DMA transfer end
condition is detected, the DMA current source address
register (DMCSADRn) is reloaded with the value of the
DMA reload source address register (DMRSADRn).
0: Source address reload function disabled
1: Source address reload function enabled
8
DRLOD 0
R/W DMA Destination Address Reload Function Enable
This bit specifies whether or not the destination
address is reloaded when the DMA transfer end
condition is detected.
When this bit is cleared to "0", reloading is not re-
executed.
When this bit is set to "1" and the DMA transfer end
condition is detected, the DMA current destination
address register (DMCDADRn) is reloaded with the
value of the DMA reload destination address register
(DMRDADRn).
0: Destination address reload function disabled
1: Destination address reload function enabled
7, 6

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 327 of 1312
REJ09B0320-0200