SH7261 Datasheet, PDF (1313/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 31 Electrical Characteristics
31.3.10 IIC3 Module Timing
Table 31.14 I²C Bus Interface 3 Timing
Conditions: PV_CC = V_CCR = PLLV_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V,
PV_CC − 0.3 V ≤ AV_CC ≤ PV_CC, AV_ref = 3.0 V to AV_CC,
PV_SS = V_SSR = PLLV_SS = AV_SS = 0 V
Specifications
Item
Symbol Test Conditions Min.
SCL input cycle time
t
SCL
SCL input high pulse width
t
SCLH
SCL input low pulse width
t
SCLL
SCL, SDA input rise time
t_Sr
SCL, SDA input fall time
t
Sf
SCL, SDA input spike pulse
t
SP
removal time*²
12
t *1
pcyc
+
600
3
t *1
pcyc
+
300
5
t *1
pcyc
+
300



SDA input bus free time
t_BUF
5
Start condition input hold time t
3
STAH
Retransmit start condition input t_STAS
3
setup time
Stop condition input setup time t
STOS
Data input setup time
t
SDAS
Data input hold time
t_SDAH
SCL, SDA capacitive load
Cb
3
1
t *1
pcyc
+
20
0
0
SCL, SDA output fall time*³
t
of
PV = 3.0 to 3.6 V —
CC
Notes: 1. t_pcyc indicates the peripheral clock (Pφ) cycle.
2. Depends on the value of NF2CYC.
3. Indicates the I/O buffer characteristics.
Typ.














Max.



300
300
1.2






400
250
Unit Figure
ns Figure 31.33
ns
ns
ns
ns
t *¹
pcyc
t *1
pcyc
t *1
pcyc
t *1
pcyc
t *1
pcyc
ns
ns
pF
ns
Rev. 2.00 Sep. 07, 2007 Page 1281 of 1312
REJ09B0320-0200