SH7261 Datasheet, PDF (364/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.9 DMA Control Register B (DMCNTB)
DMCNTB enables or disables DMA transfer, clears the DMA transfer enable bit, and also clears
the internal state. In addition, this register can check the status of a DMA request.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — DEN — — — — — — — DREQ
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R/W R R R R R R R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — ECLR — — — — — — — DSCLR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R/W R R R R R R R R/W
Bit
Bit Name
31 to 25 
Initial
Value
All 0
24
DEN
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W DMA Transfer Enable
This bit is used to enable or disable DMA transfer on
the corresponding channel.
Clearing this bit to "0" disables DMA transfer.
Setting this bit to "1" enables DMA transfer. For the
activation of DMA transfer, see section 11.4.3, DMA
Activation.
Even when this bit is clear, the input of a DMA request
to the DMAC can change the value of the DMA
request bit (DREQ).
When the DMA transfer enable clear bit (ECLR) is set
to "1", this bit is automatically cleared to "0" on
detection of the DMA transfer end condition.
Clearing this bit to "0" during DNA transfer can be
used to stop channel operation at the end of the
current single operand transfer. For details, see
section 11.6, Suspending, Restarting, and Stopping of
DMA Transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Rev. 2.00 Sep. 07, 2007 Page 332 of 1312
REJ09B0320-0200