SH7261 Datasheet, PDF (367/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Initial
Bit
Bit Name Value
16
DREQ
0
15 to 9 
All 0
Section 11 Direct Memory Access Controller (DMAC)
R/W Description
R/W (c) When a source other than the software trigger is
selected (DCTG = "000000") by the DMA request
source selection bits (DCTG) and an edge sense
has been selected
• Condition for setting to "1"
The DREQ bit is set to "1" when the edge specified
by the input sense selection bits (STRG) is
encountered, i.e. when a DMA request exists.
Once this bit has been set to "1", regardless of the
subsequent state of the DMA request signal, the
DMA request bit (DREQ) remains set until a
condition for clearing to "0" has been satisfied.
• Condition for clearing to "0"
This bit is cleared to "0" by either of the events
listed below.
 Software writing a "0" to this bit
 The start of operand transfer corresponding to
the bit
Notes: 1. In a case where a source other than
software triggering is selected, do not write
"1" to the DMA request bit (DREQ). If "1" is
written to this bit, operation is not
guaranteed.
2. After setting the DMA request source
selection bits (DCTG) and the input sense
mode selection bits (STRG) in DMA control
register A (DMCNTAn), be sure to clear the
DMA request bit (DREQ) for the channel to
"0" and enable DMA transfer (DMST = "1"
and DEN = "1").
0: No DMA request
1: DMA requested
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 335 of 1312
REJ09B0320-0200