SH7261 Datasheet, PDF (1046/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 22 A/D Converter (ADC)
22.3 Register Configuration
The A/D converter has the following registers.
Table 22.2 Register Configuration
Register Name
Abbreviation R/W
A/D data register A
ADDRA
R
A/D data register B
ADDRB
R
A/D data register C
ADDRC
R
A/D data register D
ADDRD
R
A/D data register E
ADDRE
R
A/D data register F
ADDRF
R
A/D data register G
ADDRG
R
A/D data register H
ADDRH
R
A/D control/status register ADCSR
R/W
Initial
Value
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0040
Address
H'FFFE5800
H'FFFE5802
H'FFFE5804
H'FFFE5806
H'FFFE5808
H'FFFE580A
H'FFFE580C
H'FFFE580E
H'FFFE5820
Access
Size
16
16
16
16
16
16
16
16
16
22.3.1 A/D Data Registers A to H (ADDRA to ADDRH)
The sixteen A/D data registers, ADDRA to ADDRH, are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the ADDR
corresponding to the selected channel. The 10 bits of the result are stored in the upper bits (bits 15
to 6) of ADDR. Bits 5 to 0 of ADDR are reserved bits that are always read as 0.
Access to ADDR in 8-bit units is prohibited. ADDR must always be accessed in 16-bit units.
ADDR is initialized to H'0000 by a power-on reset as well as in deep standby mode, software
standby mode or module standby mode.
Rev. 2.00 Sep. 07, 2007 Page 1014 of 1312
REJ09B0320-0200