SH7261 Datasheet, PDF (257/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value
R/W Description
6 to 4 CSWOFF 000
[2:0]
R/W Write Operation CS Delay Cycle Select
These bits specify the number of cycles from the end of
the wait cycle during write access operation (negation
of the WR3 to WR0 signals) and the negation of the
CS6 to CS0 signal.
000: 0 wait state
:
111: 7 wait states
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0 CSROFF 111
[2:0]
R/W Read Operation CS Delay Cycle Select
These bits specify the number of cycles from the end of
the wait cycle during read access operation (negation
of the RD signal) and the negation of the CS6 to CS0
signal.
000: 0 wait state
:
111: 7 wait states
Notes: 1. Select each wait cycle number or extended cycle number according the system
configuration incorporated.
2. Writing to the CSn wait control register 2 (CS2WCNTn) must be done while CSC for the
corresponding channel is disabled (EXENB = 0). Only channel 0 (CS0) can be enabled
by setting EXENB = 1. To enable channel 0, stop the DMAC and set EXENB to 1
between the reset release and data write access to CS0.
3. Each bit must be set under the following restrictions.
• When page access is disabled (PRENB, PWENB = 0)
CSON ≤ min (CSRWAIT, CSWWAIT), WDON ≤ CSWWAIT
WRON ≤ CSWWAIT, RDON ≤ CSRWAIT
WDOFF ≤ CSWOFF
• When page access is enabled (PRENB = 1 or PWENB = 1)
In addition to the restrictions for disabled page access case, the following
restrictions are required.
CSON ≤ min (CSPRWAIT, CSPWWAIT)
WRON ≤ CSPWWAIT, RDON ≤ CSPRWAIT
WDON ≤ CSPWWAIT
Rev. 2.00 Sep. 07, 2007 Page 225 of 1312
REJ09B0320-0200