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SH7261 Datasheet, PDF (1161/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Section 27 Power-Down Modes
27.2.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. STBCR2 is initialized to H'1E by a power-on reset or in deep standby mode but
retains its previous value by a manual reset or in software standby mode. Only byte access is valid.
Note: When writing to this register, see section 27.4, Usage Note.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
10 9
8
7
6
5
4
3
Initial value: 0
0
0
1
1
1
1
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
MSTP10 0
R/W Module Stop 10
When the MSTP10 bit is set to 1, the supply of the
clock to the H-UDI is halted.
0: H-UDI runs.
1: Clock supply to H-UDI halted.
6
MSTP9
0
R/W Module Stop 9
When the MSTP9 bit is set to 1, the supply of the clock
to the UBC is halted.
0: UBC runs.
1: Clock supply to UBC halted.
5
MSTP8
0
R/W Module Stop 8
When the MSTP8 bit is set to 1, the supply of the clock
to the DMAC is halted.
0: DMAC runs.
1: Clock supply to DMAC halted.
4
MSTP7
1
R/W Module Stop 7
When the MSTP7 bit is set to 1, the supply of the clock
to the ROM-DEC is halted.
0: ROM-DEC runs.
1: Clock supply to ROM-DEC halted.
Rev. 2.00 Sep. 07, 2007 Page 1129 of 1312
REJ09B0320-0200