SH7261 Datasheet, PDF (57/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Initial
Bit
Bit Name Value R/W
31 to 15 —
All 0 R
14
BO
13
CS
0
R/W
0
R/W
12 to 10 —
All 0 R
9
M
8
Q
7 to 4
3, 2
I[3:0]
—
—
R/W
—
R/W
1111 R/W
All 0 R
1
S
0
T
—
R/W
—
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
BO Bit
Indicates that a register bank has overflowed.
CS Bit
Indicates that, in CLIP instruction execution, the value
has exceeded the saturation upper-limit value or fallen
below the saturation lower-limit value.
Reserved
These bits are always read as 0. The write value
should always be 0.
M Bit
Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
Interrupt Mask Level
Reserved
These bits are always read as 0. The write value
should always be 0.
S Bit
Specifies a saturation operation for a MAC instruction.
T Bit
True/false condition or carry/borrow bit
Rev. 2.00 Sep. 07, 2007 Page 25 of 1312
REJ09B0320-0200