SH7261 Datasheet, PDF (633/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
Section 13 8-Bit Timers (TMR)
This LSI has an on-chip 2-channel 8-bit timer based on an 8-bit counter. It can be used to count
external events and, using compare-match signals with two registers, as a multifunction timer in a
variety of applications, such as the generation of counter resets, interrupt requests, and pulse
output with a user-defined duty cycle.
Figure 13.1 shows a block diagram of the 8-bit timer.
13.1 Features
• Selection of seven clock sources
The counters can be driven by one of six internal clock signals (Pφ/8, Pφ/64, Pφ/8192, Pφ/2,
Pφ/32, or Pφ/1024) or an external clock input.
• Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or by an external reset signal.
• Timer output control by a combination of two compare match signals
The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to output pulses with a desired duty cycle or PWM
output.
• Cascading of two channels (TMR_0 and TMR_1)
Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the
lower 8 bits (16-bit count mode).
TMR_1 can be used to count TMR_0 compare matches (compare match count mode).
• Three interrupt sources
Compare match A, compare match B, and overflow interrupts can be requested independently.
• Generation of trigger to start A/D converter conversion
Rev. 2.00 Sep. 07, 2007 Page 601 of 1312
REJ09B0320-0200