SH7261 Datasheet, PDF (145/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 5 Exception Handling
5.7.5 Integer Division Instructions
When an integer division instruction performs division by zero or the result of integer division
overflows, integer division instruction exception handling starts. The instructions that may become
the source of division-by-zero exception are DIVU and DIVS. The only source instruction of
overflow exception is DIVS, and overflow exception occurs only when the negative maximum
value is divided by −1. The CPU operates as follows:
1. The exception service routine start address which corresponds to the integer division
instruction exception that occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
integer division instruction at which the exception occurred.
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
5.7.6 Floating-point Operation Instruction
When the bits V, Z, O, U, or I in the enabled field of the floating point status/control register
(FPSCR) are set, a FPU exception is generated. This means that instructions that cause disabled
operation exception defined by IEEE754 standard, division exception by zero, overflow (possible
instruction), underflow (possible instruction), or imprecise exception (possible instruction) are
yielded. Floating-point operation instructions that can be exception sources are FADD, FSUB,
FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, and
FSQRT.
FPU exceptions occur only when the said enabled bits are set. When the FPU detects exception
sources, the FPU operation stops and exception occurrence is notified to the CPU. The CPU starts
the exception handling as follows:
1. The exception service routine start address which corresponds to the FPU exception that
occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
Rev. 2.00 Sep. 07, 2007 Page 113 of 1312
REJ09B0320-0200