SH7261 Datasheet, PDF (76/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Classification
Logic
operations
Shift
Branch
Types
6
12
10
Operation
Code
AND
NOT
OR
TAS
TST
XOR
ROTL
ROTR
ROTCL
ROTCR
SHAD
SHAL
SHAR
SHLD
SHLL
SHLLn
SHLR
SHLRn
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
RTV/N
Function
No. of
Instructions
Logical AND
14
Bit inversion
Logical OR
Memory test and bit set
Logical AND and T bit set
Exclusive OR
One-bit left rotation
16
One-bit right rotation
One-bit left rotation with T bit
One-bit right rotation with T bit
Dynamic arithmetic shift
One-bit arithmetic left shift
One-bit arithmetic right shift
Dynamic logical shift
One-bit logical left shift
n-bit logical left shift
One-bit logical right shift
n-bit logical right shift
Conditional branch, conditional delayed branch 15
(branch when T = 0)
Conditional branch, conditional delayed branch
(branch when T = 1)
Unconditional delayed branch
Unconditional delayed branch
Delayed branch to subroutine procedure
Delayed branch to subroutine procedure
Unconditional delayed branch
Branch to subroutine procedure
Delayed branch to subroutine procedure
Return from subroutine procedure
Delayed return from subroutine procedure
Return from subroutine procedure with Rm →
R0 transfer
Rev. 2.00 Sep. 07, 2007 Page 44 of 1312
REJ09B0320-0200