SH7261 Datasheet, PDF (950/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
Initial
Bit
Bit Name Value R/W Description
2
TXETTMEE 0
R/W Transmit Timing Error Interrupt Enable
Enables/disables a transmit timing error (TXETTMEE)
interrupt.
0: Disables a transmit timing error (TXETTMEE)
interrupt
1: Enables a transmit timing error (TXETTMEE)
interrupt
1
TXEROE 0
R/W Overflow of Maximum Number of Transmit Bytes in
One Frame Interrupt Enable
Enables/disables an overflow of the maximum number
of transmit bytes in one frame (TXEROE) interrupt.
0: Disables an overflow of the maximum number of
transmit bytes in one frame (TXEROE) interrupt
1: Enables an overflow of the maximum number of
transmit bytes in one frame (TXEROE) interrupt
0
TXEACKE 0
R/W Acknowledge Bit Interrupt Enable
Enables/disables an acknowledge bit (TXEACKE)
interrupt.
0: Disables an acknowledge bit (TXEACKE) interrupt
1: Enables an acknowledge bit (TXEACKE) interrupt
Rev. 2.00 Sep. 07, 2007 Page 918 of 1312
REJ09B0320-0200