SH7261 Datasheet, PDF (588/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation is the data before write.
Figure 12.112 shows the timing in this case.
Pφ
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N
M
TGR
N
Figure 12.112 Contention between Buffer Register Write and Compare Match
Rev. 2.00 Sep. 07, 2007 Page 556 of 1312
REJ09B0320-0200