SH7261 Datasheet, PDF (423/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
5
BFB
0
R/W Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated in other than complementary PWM mode.
TGRD compare match is generated in complementary
PWM mode. When compare match occurs during the tb
period in complementary PWM mode, TGRD is set.
Therefore, set the TGIED bit in the timer interrupt
enable register_3/4 (TIER_3/4) to 0.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer operation
4
BFA
0
R/W Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated in other than complementary PWM mode.
TGRC compare match is generated in complementary
PWM mode. When compare match for channel 4
occurs during the tb period in complementary PWM
mode, TGFC is set. Therefore, set the TGIEC bit in the
timer interrupt enable register_4 (TIER_4) to 0.
In channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA and TGRC operate normally
1: TGRA and TGRC used together for buffer operation
3 to 0 MD[3:0]
0000 R/W Modes 0 to 3
These bits are used to set the timer operating mode.
See table 12.11 for details.
Rev. 2.00 Sep. 07, 2007 Page 391 of 1312
REJ09B0320-0200