SH7261 Datasheet, PDF (389/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Cycle-stealing transfer mode
One DMA transfer
Single operand transfer (read 1 wait)
Single operand transfer (read 1 wait)
CKIO
DMA (S)
DMA (D)
DACK
DTEND (00)
DTEND (01)
DTEND (10)
DTEND (11)
DMINT_N
RD1
High
WR1
RD2
WR2
RD1
WR1
RD2
WR2
DTCM setting
Pipelined transfer mode
One DMA transfer
Last read Last write End of
of one DMA of one DMA one DMA
transfer
transfer
transfer
Single operand transfer (read 0 wait)
Single operand transfer (read 0 wait)
CKIO
DMA (S)
DMA (D)
RD1 RD2 RD3 RD4
WR1 WR2 WR3 WR4
RD1 RD2 RD3 RD4
WR1 WR2 WR3 WR4
DACK
DTEND (00)
High
DTEND (01)
DTEND (10)
DTEND (11)
DMINT_N
DTCM setting
[Legend]
DMA (S): Internal access cycle on DMAC source side
DMA (D): Internal access cycle on DMAC destination side
Last read Last write End of
of one DMA of one DMA one DMA
transfer
transfer
transfer
Figure 11.5 Timing of DMA End Signal Output
Rev. 2.00 Sep. 07, 2007 Page 357 of 1312
REJ09B0320-0200