SH7261 Datasheet, PDF (379/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Cycle steal transfer mode (transfer between different BIU)
System clock
Single operand transfer
Single operand transfer
DMAC
CPU
Read
Read
Write
Write
Read
Read
Write
Write
(1)
(2) (1)
(2)
(1)
(2) (1)
(2)
(1) CPU access to other than BIU on DMAC read side is possible
(2) CPU access to other than BIU on DMAC write side is possible
Cycle steal transfer mode (transfer in the same BIU)
System clock
Single operand transfer
Single operand transfer
DMAC
CPU
Read
Read
Write
Write
Read
Read
Write
Write
(3)
(3)
(3)
(3)
(3)
(3)
(3) CPU access to other than BIU on DMAC read/write side is possible
Pipeline transfer mode (transfer between different BIU)
System clock
Single operand transfer
Single operand transfer
DMAC
CPU
Read Read Read Read
Write Write Write Write
Read Read Read Read
Write Write Write Write
(4)
(5)
(6)
(4)
(5)
(6)
(4) CPU access to other than BIU on DMAC read side is possible
(5) CPU access to other than BIU on DMAC read/write side is possible
(6) CPU access to other than BIU on DMAC write side is possible
Figure 11.2 Examples of the Alternation of Bus Mastership between the DMAC
and CPU in Various DMA Transfer Modes
Rev. 2.00 Sep. 07, 2007 Page 347 of 1312
REJ09B0320-0200