SH7261 Datasheet, PDF (217/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
11. Do not set a pre-execution break and a break after instruction execution simultaneously in one
address. For example, if a pre-execution break for channel 0 and a break after instruction
execution for channel 1 are set simultaneously for one address, a break generated prior to
instruction execution for channel 0 can set a condition-match flag after the instruction
execution for channel 1.
Rev. 2.00 Sep. 07, 2007 Page 185 of 1312
REJ09B0320-0200