SH7261 Datasheet, PDF (393/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
clock) after the end of the single operand transfer. This provides a margin in which continued
requests for DMA transfer on the same channel are rejected.
Figure 11.8 shows the period over which DMA request bit is masked when a level sense has been
selected.
System clock
DMA state
DMA request input
(low level sense)
Single operand transfer
Start of channel arbitration
Read
Write
DMA acknowledge
output
DMA request bit
[Legend]
: Sampling point for DMA requests
(Period of masking for the DMA request bit)
The period of the unit transfer operation in this example is short;
non-recognition of the DMA request during the masking period prevents a DMA
request that is cleared too late from affecting the next channel-arbitration period.
Figure 11.8 Period over which DMA Request Bit is Masked
when a Level Sense is Selected
Therefore, for a channel on which level sense has been selected, even when the DMA request
signal level is maintained (requesting further DMA transfer) well after the DMA request has been
accepted and handled, DMA requests on other channels, if they exist, are accepted. This is because
the DMA request on the channel on which level sense has been selected is not considered to exist
during the DMA request bit masking period.
In the case of sequential operand transfer, masking is only applied from the end of operand
transfer, i.e. when the byte count is 0. The DMA request is not masked while the byte count is
non-zero, so channel arbitration is executed without masking of the DMA request during the
actual unit transfer operation.
In the case of non-stop transfer, masking is only enabled from the end of the transfer operation, i.e.
when the byte count is 0.
Rev. 2.00 Sep. 07, 2007 Page 361 of 1312
REJ09B0320-0200