SH7261 Datasheet, PDF (274/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Bit
3 to 0
Bit Name
Initial
Value
ACOSW[3:0] 0000
R/W Description
R/W AC Characteristics Switch
These bits specify AC characteristics switching.
0000: Does not extend the delay time
0011: Switches characteristics and extends the delay
time
Other than above: Setting prohibited
9.5 Operation
9.5.1 CSC Interface
(1) Normal Access
Normal read/write operation is used for all bus access when page read/write access is disabled
(PRENB = 0, PWENB = 0). Even when page read/write access is enabled (PRENB = 1, PWENB
= 1), normal read/write operation is employed in cases where page access cannot be used. Figure
9.2 shows the basic operation of the external bus control signals in read operation, and figure 9.3
shows the basic operation of these signals in write operation.
CKIO
A27 to A0
CSn
RD
WR
D31 to D0
Ts Tw1 Tw2
Twn Tend Tn1 Tn2
(Trd)
Tnm
Read cycle wait
CS assert wait
RD assert wait
Start enable point
of next bus access
CS delay
cycle during read
Figure 9.2 Basic Bus Timing (Read Operation)
Rev. 2.00 Sep. 07, 2007 Page 242 of 1312
REJ09B0320-0200