SH7261 Datasheet, PDF (72/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Instruction Formats
nmd format
15
0
xxxx nnnn mmmm dddd
nmd12 format
32
16
xxxx nnnn mmmm xxxx
15
0
xxxx dddd dddd dddd
d format
15
0
xxxx xxxx dddd dddd
d12 format
15
0
xxxx dddd dddd dddd
nd8 format
15
0
xxxx nnnn dddd dddd
i format
15
0
xxxx xxxx iiii iiii
Source
Operand
Destination
Operand
Example
mmmm: Register
direct
nnnndddd: Register MOV.L
indirect with
Rm,@(disp,Rn)
displacement
mmmmdddd:
Register indirect
with displacement
nnnn: Register
direct
MOV.L
@(disp,Rm),Rn
mmmm: Register
direct
nnnndddd: Register MOV.L
indirect with
Rm,@(disp12,Rn)
displacement
mmmmdddd:
Register indirect
with displacement
nnnn: Register
direct
MOV.L
@(disp12,Rm),Rn
dddddddd: GBR
indirect with
displacement
R0 (Register direct) MOV.L
@(disp,GBR),R0
R0 (Register direct) dddddddd: GBR
indirect with
displacement
MOV.L
R0,@(disp,GBR)
dddddddd: PC
relative with
displacement
R0 (Register direct) MOVA
@(disp,PC),R0
dddddddd: TBR —
duplicate indirect
with displacement
JSR/N
@@(disp8,TBR)
dddddddd: PC
—
relative
BF
label
dddddddddddd: PC —
relative
BRA label
(label = disp +
PC)
dddddddd: PC
relative with
displacement
nnnn: Register
direct
MOV.L
@(disp,PC),Rn
iiiiiiii: Immediate
Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
iiiiiiii: Immediate
iiiiiiii: Immediate
R0 (Register direct) AND #imm,R0
—
TRAPA #imm
Rev. 2.00 Sep. 07, 2007 Page 40 of 1312
REJ09B0320-0200