SH7261 Datasheet, PDF (551/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(o) Counter Clearing by TGRA_3 Compare Match
In complementary PWM mode, by setting the CCE bit in the timer waveform control register
(TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare
match.
Figure 12.62 illustrates an operation example.
Notes: 1. Use this function only in complementary PWM mode 1 (transfer at crest).
2. Do not specify synchronous clearing by another channel (do not set the SYNC0 to
SYNC4 bits in the timer synchronous register (TSYR) to 1).
3. Do not set the PWM duty value to H'0000.
4. Do not set the PSYE bit in timer output control register 1 (TOCR1) to 1.
TGRA_3
Counter cleared
by TGRA_3 compare match
TCDR
TGRB_3
TDDR
H'0000
Output waveform
Output waveform
Output waveform is active-high.
Figure 12.62 Example of Counter Clearing Operation by TGRA_3 Compare Match
Rev. 2.00 Sep. 07, 2007 Page 519 of 1312
REJ09B0320-0200