SH7261 Datasheet, PDF (693/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Realtime Clock (RTC)
15.3.18 RTC Control Register 3 (RCR3)
When the ENB bit in RCR3 is set to 1, RCR3 compares the value of RYRCNT and that of
RYRAR. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the
counter and alarm register comparison is performed only on those with ENB bits set to 1, and if
each of those coincides, an alarm flag of RCR1 is set to 1.
The ENB bit in RCR3 is initialized by a power-on reset or in deep standby mode. Remaining
fields of RCR3 are not initialized by a power-on reset or manual reset, or in deep standby and
software standby modes.
Bit: 7
6
5
4
3
2
1
0
ENB — — — — — — —
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R
Initial
Bit Bit Name Value
7
ENB
0
6 to 0 
All 0
R/W Description
R/W When this bit is set to 1, comparison of the year alarm
register (RYRAR) and the year counter (RYRCNT) is
performed.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 661 of 1312
REJ09B0320-0200