SH7261 Datasheet, PDF (320/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
This LSI
A16
A15
A14
A13 to A2
A1, A0
SDCKE
SDCLK
SDCS
SDRAS
SDCAS
SDWE
D13 to D16
DQM3
DQM2
D15 to D0
DQM1
DQM0
Not in use
Not in use
Not in use
Not in use
Not in use
64 M SDRAM
(1 M × 16 bits × 4 banks)
A13 (BA1)
A12 (BA0)
A11 to A0
CKE
CLK
CS
RAS
CAS
WE
I/O15 to I/O0
DQMU
DQML
Figure 9.43 Example of Connecting a 16-Bit Data-Width SDRAM
9.6 Usage Note
9.6.1 Note on Power-on Reset Exception Handling and Deep Standby Mode Cancellation
When writing to the external address space or making SDRAM settings in power-on reset
exception handling or cancellation of deep standby mode, be sure to set bits ACOSW[3:0] in
ACSWR to B'0011 beforehand.
9.6.2 Write Buffer
In write access to normal or SDRAM space, the write data are stored once in the internal write
buffer of the BSC, and only after that does actual writing to the device (external device) connected
in the normal or SDRAM space proceed. Since writing from the write buffer to the external device
is performed automatically, no processing by software is necessary.
However, care must be taken on the following point. Write access from the CPU or DMAC
appears complete at the point where the data are stored in the above write buffer. That is, at the
point where the write access from the CPU or DMA controller has been completed, writing to the
external device might not have been completed. To confirm the completion of writing to the
external device, dummy read the normal or SDRAM space. Completion of the dummy-read
operation guarantees the completion of writing to the external device in response to previous write
Rev. 2.00 Sep. 07, 2007 Page 288 of 1312
REJ09B0320-0200