SH7261 Datasheet, PDF (27/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

21.3.47 CD-ROM Decoder Reset Status Register (RSTSTAT) ........................................ 985
21.3.48 SSI Data Control Register (SSI) ........................................................................... 985
21.3.49 Interrupt Flag Register (INTHOLD)..................................................................... 988
21.3.50 Interrupt Source Mask Control Register (INHINT).............................................. 989
21.3.51 Buffer Control Register (RINGBUFCTL) ............................................................ 990
21.3.52 CD-ROM Decoder Stream Data Input Register (STRMDIN0) ............................ 991
21.3.53 CD-ROM Decoder Stream Data Input Register (STRMDIN1) ............................ 991
21.3.54 CD-ROM Decoder Stream Data Input Register (STRMDIN2) ............................ 992
21.3.55 CD-ROM Decoder Stream Data Input Register (STRMDIN3) ............................ 992
21.3.56 CD-ROM Decoder Stream Data Output Register (STRMDOUT0)...................... 993
21.3.57 CD-ROM Decoder Stream Data Output Register (STRMDOUT1)...................... 993
21.4 Operation ........................................................................................................................... 994
21.4.1 Endian Conversion for Data in the Input Stream .................................................. 994
21.4.2 Sync Code Maintenance Function ........................................................................ 995
21.4.3 Error Correction.................................................................................................. 1000
21.4.4 Automatic Decoding Stop Function.................................................................... 1001
21.4.5 Buffering Format ................................................................................................ 1002
21.4.6 Target-Sector Buffering Function....................................................................... 1004
21.5 Interrupt Sources.............................................................................................................. 1006
21.5.1 Interrupt and DMA Transfer Request Signals .................................................... 1006
21.5.2 Timing of Status Registers Updates.................................................................... 1008
21.6 Usage Notes ..................................................................................................................... 1008
21.6.1 Stopping and Resuming Buffering Alone During Decoding .............................. 1008
21.6.2 When CROMST0 Status Register Bits are Set ................................................... 1008
21.6.3 Link Blocks......................................................................................................... 1008
21.6.4 Reading from the STRMDOUT0 and STRMDOUT1 Registers ........................ 1009
21.6.5 Stopping and Resuming CD-DSP Operation ...................................................... 1010
Section 22 A/D Converter (ADC)....................................................................1011
22.1 Features............................................................................................................................ 1011
22.2 Input/Output Pins ............................................................................................................. 1013
22.3 Register Configuration..................................................................................................... 1014
22.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ............................................ 1014
22.3.2 A/D Control/Status Register (ADCSR) .............................................................. 1016
22.4 Operation ......................................................................................................................... 1020
22.4.1 Single Mode........................................................................................................ 1020
22.4.2 Multi Mode ......................................................................................................... 1023
22.4.3 Scan Mode .......................................................................................................... 1025
22.4.4 A/D Converter Activation by External Trigger, MTU2, or TMR....................... 1028
22.4.5 Input Sampling and A/D Conversion Time ........................................................ 1028
Rev. 2.00 Sep. 07, 2007 Page xxvii of xxxii