SH7261 Datasheet, PDF (58/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
(2) Global Base Register (GBR)
GBR is referenced as the base address in a GBR-referencing MOV instruction.
(3) Vector Base Register (VBR)
VBR is referenced as the branch destination base address in the event of an exception or an
interrupt.
(4) Jump Table Base Register (TBR)
TBR is referenced as the start address of a function table located in memory in a
JSR/N@@(disp8,TBR) table-referencing subroutine call instruction.
2.1.3 System Registers
The system registers consist of four 32-bit registers: the high and low multiply and accumulate
registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH
and MACL store the results of multiply or multiply and accumulate operations. PR stores the
return address from a subroutine procedure. PC indicates the program address being executed and
controls the flow of the processing.
31
MACH
MACL
31
PR
0 _{Multiply and accumulate register high (MACH) and multiply}
and accumulate register low (MACL):
Store the results of multiply or multiply and accumulate operations.
0 _{Procedure register (PR):}
Stores the return address from a subroutine procedure.
31
PC
0 _{Program counter (PC):}
Indicates the four bytes ahead of the current instruction.
Figure 2.3 System Registers
(1) Multiply and Accumulate Register High (MACH) and Multiply and Accumulate
Register Low (MACL)
MACH and MACL are used as the addition value in a MAC instruction, and store the result of a
MAC or MUL instruction.
Rev. 2.00 Sep. 07, 2007 Page 26 of 1312
REJ09B0320-0200