SH7261 Datasheet, PDF (654/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
13.8.5 Conflict between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 13.4.
Table 13.4 Timer Output Priorities
Output Setting
Toggle output
1-output
0-output
No change
Priority
High
Low
13.8.6 Switching of Internal Clocks and TCNT Operation
TCNT may be incremented erroneously depending on when the internal clock is switched. Table
13.5 shows the relationship between the timing at which the internal clock is switched (by writing
to bits CKS1 and CKS0) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the rising or falling edge of the internal
clock pulse are always monitored. Table 13.5 assumes that the falling edge is selected. If the
signal levels of the clocks before and after switching change from high to low as shown in item 3,
the change is considered as the falling edge. Therefore, a TCNT clock pulse is generated and
TCNT is incremented. This is similar to when the rising edge is selected.
The erroneous incrementation of TCNT can also happen when switching between rising and
falling edges of the internal clock, and when switching between internal and external clocks.
Rev. 2.00 Sep. 07, 2007 Page 622 of 1312
REJ09B0320-0200