SH7261 Datasheet, PDF (1017/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.47 CD-ROM Decoder Reset Status Register (RSTSTAT)
RSTSTAT indicates that the RAM in the CD-ROM decoder has been cleared.
Bit: 7
6
5
4
3
2
1
0
RAM
CLRST
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit Bit Name
7
RAMCLRST
6 to 0 
Initial
Value
0
All 0
R/W Description
R
This bit is set to 1 on the completion of RAM clearing
triggered by setting RAMRST to 1. It is cleared by
writing a 0 to RAMRST.
R
Reserved
These bits are always read as 0 and cannot be
modified.
21.3.48 SSI Data Control Register (SSI)
SSI provides various settings related to the data stream. For the operation corresponding to the
setting of this register, see section 21.4.1, Endian Conversion for Data in the Input Stream.
Bit: 7
6
5
4
3
2
1
0
BYTEND BITEND BUFEND0[1:0] BUFEND1[1:0] —
—
Initial value: 0
0
0
1
1
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
7
BYTEND
6
BITEND
Initial
Value
0
0
R/W Description
R/W Specifies the endian of input data from the SSI module.
When this bit is set to 1, the bytes in STRMDIN0 and
STRMDIN1 are swapped, as are those in STRMDIN2
and STRMDIN3.
R/W Specifies treatment of the bit order of the input data
from the SSI module.
When this bit is set to 1, the bits within each byte are
rearranged to place them in reverse order, bit 0 → bit 7
to bit 7 → bit 0.
Rev. 2.00 Sep. 07, 2007 Page 985 of 1312
REJ09B0320-0200