SH7261 Datasheet, PDF (336/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus Monitor
(2) DMAC Transfer Modes and Operations of Each Bus
Table 10.7 shows the DMAC transfer modes and the types of bus error that may be generated by
accesses from the DMAC.
Table 10.7 DMAC Transfer Modes and Types of Bus Error Generated
DMAC Transfer Mode
Cycle Steal
Pipeline
Illegal address access*
O
O
Bus timeout*
O
O
[Legend]
O: A bus error is generated.
: A bus error is not generated.
Note: * To enable bus error detection, the bus monitor enable register (SYCBEEN) should be
set.
10.3 Usage Note
10.3.1 Operation when the CPU is Not Notified of a Bus Error
Table 10.8 describes the operations when bus error notification to the CPU is disabled with the bus
error detection enabled (by the setting of the bus monitor enable register (SYCBEEN)).
Table 10.8 Operation When the Master is Not Notified of a Bus Error
Illegal address access
Bus timeout
Illegal address access errors equal in number to the predetermined
number of transfers are generated and the access is terminated each
time.
Bus timeouts equal in number to the predetermined number of
transfers are generated and the access is terminated each time.
Rev. 2.00 Sep. 07, 2007 Page 304 of 1312
REJ09B0320-0200