SH7261 Datasheet, PDF (872/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Bit 6 - Bus Off Interrupt Flag (IRR6): This bit is set when RCAN-ET enters the Bus-off state or
when RCAN-ET leaves Bus-off and returns to Error-Active. The cause therefore is the existing
condition TEC ≥ 256 at the node or the end of the Bus-off recovery sequence (128 × 11
consecutive recessive bits) or the transition from Bus Off to Halt (automatic or manual). This bit
remains set even if the RCAN-ET node leaves the bus-off condition, and needs to be explicitly
cleared by S/W. The S/W is expected to read the GSR0 to judge whether RCAN-ET is in the bus-
off or error active status. It is cleared by writing a '1' to this bit position even if the node is still
bus-off. Writing a '0' has no effect.
Bit 6: IRR6
0
1
Description
[Clearing condition] Writing 1 (Initial value)
Enter Bus off state caused by transmit error or Error Active state returning
from Bus-off
[Setting condition] When TEC becomes ≥ 256 or End of Bus-off after 128×
11 consecutive recessive bits or transition from Bus Off to Halt
Bit 5 - Error Passive Interrupt Flag (IRR5): Interrupt flag indicating the error passive state
caused by the transmit or receive error counter or by Error Passive forced by test mode. This bit is
reset by writing a '1' to this bit position, writing a '0' has no effect. If this bit is cleared the node
may still be error passive. Please note that the SW needs to check GSR0 and GSR5 to judge
whether RCAN-ET is in Error Passive or Bus Off status.
Bit 5: IRR5
0
1
Description
[Clearing condition] Writing 1 (Initial value)
Error passive state caused by transmit/receive error
[Setting condition] When TEC ≥ 128 or REC ≥ 128 or Error Passive test
mode is used
Bit 4 - Receive Error Counter Warning Interrupt Flag (IRR4): This bit becomes set if the
receive error counter (REC) reaches a value greater than 95 when RCAN-ET is not in the Bus Off
status. The interrupt is reset by writing a '1' to this bit position, writing '0' has no effect.
Bit 4: IRR4
0
1
Description
[Clearing condition] Writing 1 (Initial value)
Error warning state caused by receive error
[Setting condition] When REC ≥ 96 and RCAN-ET is not in Bus Off
Rev. 2.00 Sep. 07, 2007 Page 840 of 1312
REJ09B0320-0200