SH7261 Datasheet, PDF (492/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4 Operation
12.4.1 Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, cycle counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Always select MTU2 external pins set function using the pin function controller (PFC).
(1) Counter Operation
When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in TSTR_5 is set
to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a
free-running counter, periodic counter, for example.
(a) Example of Count Operation Setting Procedure
Figure 12.4 shows an example of the count operation setting procedure.
Operation selection
Select counter clock [1]
Periodic counter
Select counter clearing _[2]
source
Select output compare _[3]
register
Set period
[4]
Start count operation [5]
<Periodic counter>
Free-running counter
Start count operation [5]
<Free-running counter>
[1] Select the counter clock
with bits TPSC2 to TPSC0
in TCR. At the same time,
select the input clock edge
with bits CKEG1 and
CKEG0 in TCR.
[2] For periodic counter
operation, select the TGR
to be used as the TCNT
clearing source with bits
CCLR2 to CCLR0 in TCR.
[3] Designate the TGR
selected in [2] as an output
compare register by means
of TIOR.
[4] Set the periodic counter
cycle in the TGR selected
in [2].
[5] Set the CST bit in TSTR to
1 to start the counter
operation.
Figure 12.4 Example of Counter Operation Setting Procedure
Rev. 2.00 Sep. 07, 2007 Page 460 of 1312
REJ09B0320-0200