SH7261 Datasheet, PDF (503/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(b) When TGR is an input capture register
Figure 12.18 shows an operation example in which TGRA has been designated as an input capture
register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges
have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
TIOCA
Time
TGRA
TGRC
H'0532
H'0F07
H'09FB
H'0532
H'0F07
Figure 12.18 Example of Buffer Operation (2)
Rev. 2.00 Sep. 07, 2007 Page 471 of 1312
REJ09B0320-0200