SH7261 Datasheet, PDF (339/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
DMA request from
outside (DREQ) or
on-chip peripheral circuit
DMA end
DMA acknowledge
DMA active
DMA interrupt request
DMA common
interrupt request
CPU control
signal
DMAC Core
DMA request transfer
CPU
I/F
Memory I/F
Current
register
Reload
register
Ch0 DMA setting data
:
Chn DMA setting data
Ch0 DMA transfer data
:
Chn DMA transfer data
On-chip memory
(Work register)
Memory load/store
control
Source address
register
Destination address
register
Byte count register
Mode register
DMAC
control
circuit
Data
buffer
DMAC
control signal
DMAC
[Legend]
DMA request transfer: Arbitration of DMA requests and generation of request signal to DMAC core
CPU I/F:
Read/write control of register access from CPU
Memory I/F:
Memory access control from CPU and DMAC core
On-chip memory: Stores DMAC setting data and transfer data
Work register:
Register the DMAC core refers to (access from CPU prohibited)
DMAC control circuit: DMAC control circuit
Data buffer:
DMA data buffer
Figure 11.1 DMAC Block Diagram
11.2 Input/Output Pins
Table 11.1 Pin Configuration
Name
DREQm (m = 0 to 3)
DACKm (m = 0 to 3)
DACTm (m = 0 to 3)
DTENDm (m = 0 to 3)
I/O
Input
Output
Output
Output
Function
External request for DMA transfer
DMA acknowledgement of external request for DMA transfer
(active low)
DMA active in externally requested DMA transfer (active low)
Completion of externally requested DMA transfer (active low)
Rev. 2.00 Sep. 07, 2007 Page 307 of 1312
REJ09B0320-0200