SH7261 Datasheet, PDF (328/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus Monitor
Initial
Bit
Bit Name Value
31

0
30
ETO
0
29
EER
0
28 to 26 
All 0
25, 24 EMST[1:0] 00
23 to 14 
All 0
13
OER
0
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R
Timeout
This bit indicates that a timeout occurred on the
external bus when the first bus error occurred.
0: Timeout not generated
1: Timeout generated
R
Illegal Address Access
This bit indicates that an illegal address access was
made on the external bus when the first bus error
occurred.
0: Illegal address access not made
1: Illegal address access made
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Bus Master
These bits indicate the bus master that accessed the
external bus when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Illegal Address Access
These bits indicate the bus master that accessed other
buses when the first bus error occurred.
0: Illegal address access not made
1: Illegal address access made
Rev. 2.00 Sep. 07, 2007 Page 296 of 1312
REJ09B0320-0200