SH7261 Datasheet, PDF (1040/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.5.2 Timing of Status Registers Updates
The status information registers of the CD-ROM decoder are updated on each ISEC interrupt. The
sector for which information is reflected in the status registers is selected by the ER0SEL bit of the
CROMCTL4 register.
21.6 Usage Notes
21.6.1 Stopping and Resuming Buffering Alone During Decoding
When the data of the output stream are being not read out but operation of the CD-ROM decoder
has continued until the buffers are full, the BUF_NG bit in the CBUFST2 register is set to 1; after
that, the CD-ROM decoder becomes incapable of operation.
To stop buffering alone, clear the CBUF_EN bit in the CBUFCTL0 register to 0. If the automatic
buffering function is in use, clear the CBUF_AUT in the CBUFCTL0 register to 0 at the same
time. In this case, the sectors currently in the buffers must be read out.
To resume automatic buffering, set the CBUF_AUT and CBUF_EN bits in the CBUFCTL0
register at the same time.
21.6.2 When CROMST0 Status Register Bits are Set
1. When the ST_SECS bit in the CROMST0 register becomes set, stop decoding immediately
and retry from one sector before the sector that was being decoded.
2. When the ST_SECL bit in the CROMST0 register becomes set, stop decoding immediately
and retry from two sectors before the sector that was being decoded.
21.6.3 Link Blocks
The CD-ROM decoder uses the header information before ECC correction to detect link blocks.
Accordingly, an input data stream that contains an error may be erroneously detected as a link
block. To prevent this, the following measures should be implemented in software.
• During buffering (BUF_ACT = 1 in the CBUFST0 register), check the LINK_OUT1 bit in the
CROMST5 register on each ISEC interrupt. If it is set to 1, check to see if an IERR interrupt
has also occurred; if an IERR interrupt has not occurred, save the MFS values from the
HEAD20 to HEAD23 registers. If an IERR interrupt has occurred, do not save the MSF
values.
Rev. 2.00 Sep. 07, 2007 Page 1008 of 1312
REJ09B0320-0200