SH7261 Datasheet, PDF (37/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Item
Features
Direct memory access • Eight channels; external request available for four of them
controller (DMAC)
• Can be activated by software, on-chip modules, or external devices
Clock pulse
generator (CPG)
 Software; 1, internal source; 33, external source;4
• Up to 64 Mbytes can be transferred
• Maximum transfer data size
 8, 16, or 32 bits for single-data transfer
 1, 2, 4, 8, 16, 32, 64, or 128 sets of data for single operand transfer
(a transfer continues until the byte count reaches 0)
• Transfer method
 Cycle-stealing transfer (dual address transfer)
Three clock cycles per one set of data (best)
Bus released between read and write cycles
 Pipeline transfer (dual address transfer)
One clock cycle per one set of data (best)
• Addressing method
Increment, decrement, or fixed
• Three clock cycles per one set of data (best)
• Transfer modes
Single operand transfer, continuous operand transfer, and non-stop
transfer
• An interrupt is requested when the byte count reaches 0
• Reloading function
Source address, destination address, and byte count
• DMAC suspend, resume, and stop function
• DMAC forcible terminate function
• Clock mode: Input clock can be selected from external input (EXTAL
or CKIO) or crystal resonator
• Input clock can be multiplied by 16 (max.) by the internal PLL circuit
• Three types of clocks generated
CPU clock: Maximum 120 MHz
Bus clock: Maximum 60 MHz
Peripheral clock: Maximum 40 MHz
Watchdog timer
(WDT)
• On-chip one-channel watchdog timer
• A counter overflow can reset this LSI
Rev. 2.00 Sep. 07, 2007 Page 5 of 1312
REJ09B0320-0200