SH7261 Datasheet, PDF (463/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4
and TADCOBRB_4)
TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or
trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and
TADCORB_4, respectively.
TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
12.3.12 Timer Counter (TCNT)
The TCNT counters are 16-bit readable/writable counters. The MTU2 has eight TCNT counters,
one each for channels 0 to 4 and three (TCNTU_5, TCNTV_5, and TCNTW_5) for channel 5.
The TCNT counters are initialized to H'0000 by a reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.
Rev. 2.00 Sep. 07, 2007 Page 431 of 1312
REJ09B0320-0200