SH7261 Datasheet, PDF (385/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.5 Completion of DMA Transfer and Interrupts
11.5.1 Completion of DMA Transfer
When the value H'0000 0000 is transferred from the working byte count register to the DMA
current byte count register (DMCBCTn) (all data has been transferred), the DMA transfer end
condition is fulfilled and one DMA transfer is complete.
The operations following detection of the DMA transfer end condition are as follows.
• DMA transfer end condition
The DMA transfer end condition detection bit (DEDET) for the corresponding channel in the
DMA transfer end detection register (DMEDET) is set to "1".
• Interrupt request generation
An interrupt request is generated for the interrupt controller according to the settings of the
DMA interrupt control register (DMICNT) and the DMA common interrupt control register
(DMICNTA).
• Output of DMA end signal
The DMA end signal (DTENDm) is output according the setting of the DMA end signal output
control bit (DTCM) in the DMA mode register (DMMODn) for the channel.
• Clearing the DMA transfer enable bit (DEN)
If the DMA transfer enable clear bit (ECLR) in DMA control register B (DMCNTBn) is set to
"1", the DEN bit in the DMA control register B (DMCNTBn) is cleared to "0", suspending any
subsequent DMA transfer for the channel.
If the DMA transfer enable clear bit (ECLR) is clear ("0"), the DEN bit is not cleared.
• Reloading the source address register
If the DMA source address reload function enable bit (SRLOD) in the DMA control register A
(DMCNTAn) is set to "1", the DMA current source address register (DMCSADRn) is reloaded
with the value in the DMA reload source address register (DMRSADRn).
Rev. 2.00 Sep. 07, 2007 Page 353 of 1312
REJ09B0320-0200