SH7261 Datasheet, PDF (862/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Bit 4 — Halt/Sleep Status Bit (GSR4): Indicates whether the CAN engine is in the halt/sleep
state or not. Please note that the clearing time of this flag is not the same as the setting time of
IRR12.
Please note that this flag reflects the status of the CAN engine and not of the full RCAN-ET IP.
RCAN-ET exits sleep mode and can be accessed once MCR5 is cleared. The CAN engine exits
sleep mode only after two additional transmission clocks on the CAN Bus.
Bit 4: GSR4
0
1
Description
RCAN-ET is not in the Halt state or Sleep state (Initial value)
Halt mode (if MCR1 = 1) or Sleep mode (if MCR5 = 1)
[Setting condition] If MCR1 is set and the CAN bus is either in intermission or
idle or MCR5 is set and RCAN-ET is in the halt mode or RCAN-ET is moving
to Bus Off when MCR14 and MCR6 are both set
Bit 3 — Reset Status Bit (GSR3): Indicates whether the RCAN-ET is in the reset state or not.
Bit 3: GSR3
0
1
Description
RCAN-ET is not in the reset state
Reset state (Initial value)
[Setting condition] After an RCAN-ET internal reset (due to SW or HW reset)
Bit 2 — Message Transmission in progress Flag (GSR2): Flag that indicates to the CPU if the
RCAN-ET is in Bus Off or transmitting a message or an error/overload flag due to error detected
during transmission. The timing to set TXACK is different from the time to clear GSR2. TXACK
is set at the 7^th bit of End Of Frame. GSR2 is set at the 3^rd bit of intermission if there are no more
messages ready to be transmitted. It is also set by arbitration lost, bus idle, reception, reset or halt
transition.
Bit 2: GSR2
0
1
Description
RCAN-ET is in Bus Off or a transmission is in progress
[Setting condition] Not in Bus Off and no transmission in progress (Initial
value)
Rev. 2.00 Sep. 07, 2007 Page 830 of 1312
REJ09B0320-0200