SH7261 Datasheet, PDF (250/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
To disable the operation for each channel, forcibly write out data tentatively stored in internal
write buffer. The procedure is as follows:
1. Execute read access to the channel whose operation is to be disabled.
2. Then, write 0 to the EXENB bit (operation disabled).
9.4.4 CSn Mode Register (CSMODn) (n = 0 to 6)
CSMODn selects the mode for page read access and the bit boundary for page access, enables
page read/write access and external wait, and selects the mode for write access.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR
MOD
—
PBCNT[1:0] —
—
PW PR
ENB ENB
—
—
—
—
EW
ENB
—
—
WR
MOD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R/W R/W R R R/W R/W R R R R R/W R R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W Description
31
PRMOD 0
R/W Page Read Access Mode Select
This bit selects the operating mode for page read
access. Clearing PRMOD to 0 selects the normal
access compatible mode. In this mode the RD signal is
negated each time a unit of data is read and an RD
assert wait is inserted. Setting PRMOD to 1 selects the
external data read sequential assert mode. In this
mode RD is asserted continuously between page
accesses.
0: Normal access compatible mode
1: External data read sequential assert mode
30

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 218 of 1312
REJ09B0320-0200