SH7261 Datasheet, PDF (1001/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.18 Pre-ECC Correction Header: Seconds Data Register (HEAD01)
HEAD01 indicates the seconds value in the header before ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD01[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit
7 to 0
Bit Name
HEAD01[7:0]
Initial
Value
All 0
R/W Description
R
Seconds value in the header before ECC correction
21.3.19 Pre-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD02)
HEAD02 indicates the frames value (1 frame = 1/75 second) in the header before ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD02[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit
7 to 0
Bit Name
HEAD02[7:0]
Initial
Value
All 0
R/W Description
R
Frames value in the header before ECC correction
21.3.20 Pre-ECC Correction Header: Mode Data Register (HEAD03)
HEAD03 indicates the mode value in the header before ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD03[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit
7 to 0
Bit Name
HEAD03[7:0]
Initial
Value
All 0
R/W Description
R
Mode value in the header before ECC correction
Rev. 2.00 Sep. 07, 2007 Page 969 of 1312
REJ09B0320-0200