SH7261 Datasheet, PDF (981/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3 Register Descriptions
The ROM-DEC has the following registers.
Table 21.1 Register Configuration
Name
Abbreviation
ROM-DEC enable control register
CROMEN
Sync code-based synchronization control CROMSY0
register
Decoding mode control register
CROMCTL0
EDC/ECC check control register
CROMCTL1
Automatic decoding stop control register CROMCTL3
Decoding option setting control register
CROMCTL4
HEAD20 to HEAD22 representation control CROMCTL5
register
Sync code status register
CROMST0
Post-ECC header error status register
CROMST1
Post-ECC subheader error status register CROMST3
Header/subheader validity check status
register
CROMST4
Mode determination and link sector
detection status register
CROMST5
ECC/EDC error status register
CROMST6
Buffer status register
CBUFST0
Decoding stoppage source status register CBUFST1
Buffer overflow status register
CBUFST2
Pre-ECC correction header:
minutes data register
HEAD00
Pre-ECC correction header:
seconds data register
HEAD01
Pre-ECC correction header:
frames (1/75 second) data register
HEAD02
Pre-ECC correction header:
mode data register
HEAD03
Initial
R/W Value Address
Access
Size
R/W H'00 H'E8000000 8
R/W H'89 H'E8000001 8
R/W H'82 H'E8000002 8
R/W H'D1 H'E8000003 8
R/W H'00 H'E8000005 8
R/W H'00 H'E8000006 8
R/W H'00 H'E8000007 8
R
H'00 H'E8000008 8
R
H'00 H'E8000009 8
R
H'00 H'E800000B 8
R
H'00 H'E800000C 8
R
H'00 H'E800000D 8
R
H'00 H'E800000E 8
R
H'00 H'E8000014 8
R
H'00 H'E8000015 8
R
H'00 H'E8000016 8
R
H'00 H'E8000018 8
R
H'00 H'E8000019 8
R
H'00 H'E800001A 8
R
H'00 H'E800001B 8
Rev. 2.00 Sep. 07, 2007 Page 949 of 1312
REJ09B0320-0200