SH7261 Datasheet, PDF (965/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.5.4 Master Reception
Figure 20.11 shows the flowchart for master reception.
Start
Initial setting
[IESA1, IESA2 register setting]
Slave address
[IEMCR register setting]
Broadcast/normal selection
Retransfer counts
Control bits
[IECMR register setting]
Master communications
request command
Receive start interrupt
Receive error interrupt
(RXE***)
Receive start interrupt (RXS)
Interrupt processing
IERSR[RXS] clear
Receive completion
interrupt
Receive error interrupt
(RXE***)
Receive completion interrupt (RXF)
Interrupt processing
IERSR[RXF] clear
Receive data read
(IERB001 to IERB128)
IERSR[RXBSY] clear
Interrupt processing
IETSR[TXE***] clear
IERSR[RXE***] clear
End
Figure 20.11 Flowchart for Master Reception
Rev. 2.00 Sep. 07, 2007 Page 933 of 1312
REJ09B0320-0200