SH7261 Datasheet, PDF (403/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
(b) Transfer to External Devices
Maximum transfer speed from an on-chip CPU block as the source (0 wait) to an external device
(2 write cycles).
• Cycle-stealing transfer mode
4 bytes / (1 read cycle + 2 write cycles + 1 idle cycle) × 60 MHz = 60 Mbytes/sec
• Pipelined transfer mode
4 bytes / (2 write cycles)× 60 MHz = 120 Mbytes/sec
Maximum transfer speed from an external device (4 read cycles) to an on-chip CPU block source
(0 wait)
• Cycle-stealing transfer mode
4 bytes / (4 read cycles + 1 write cycle + 1 idle cycle) × 60 MHz = 39.6 Mbytes/sec
• Pipelined transfer mode
4 bytes / (4 read cycles)× 60 MHz = 60 Mbytes/sec
Maximum transfer speed from an external device (4 read cycles) to an external device (2 write
cycles)
• Cycle-stealing transfer mode
4 bytes / (4 read cycles + 2 write cycles + 1 idle cycle) × 60 MHz = 34.2 Mbytes/sec
• Pipelined transfer mode
No pipelined transfer is possible between the external devices.
Note: Access to external devices is controlled by the settings of the BSC control registers. For
details, see section 9, Bus State Controller (BSC).
11.13 Usage Note
11.13.1 Note on Making a Transition To Software Standby Mode or Deep Standby Mode
If the SLEEP instruction is executed to make a transition to software standby mode or deep
standby mode during transfer by the DMAC, the DMAC stops its operation without waiting for
the completion of the transfer. Thus, the DMA transfer is not guaranteed. Therefore, when making
a transition to software standby mode or deep standby mode, wait for the completion of the DMA
transfer or stop the DMA transfer to execute the SLEEP instruction.
Rev. 2.00 Sep. 07, 2007 Page 371 of 1312
REJ09B0320-0200