SH7261 Datasheet, PDF (771/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
Bit
3
2 to 0
Bit Name
BCWP
Initial
Value
1
BC[2:0]
000
R/W Description
R/W BC Write Protect
Controls the BC[2:0] modifications. When modifying the
BC[2:0] bits, this bit should be cleared to 0. In clocked
synchronous serial mode, the BC[2:0] bits should not
be modified.
0: When writing, values of the BC[2:0] bits are set.
1: When reading, 1 is always read.
When writing, settings of the BC[2:0] bits are invalid.
R/W Bit Counter
These bits specify the number of bits to be transferred
next. When read, the remaining number of transfer bits
is indicated. With the I²C bus format, the data is
transferred with one addition acknowledge bit. Should
be made between transfer frames. If these bits are set
to a value other than B'000, the setting should be made
while the SCL pin is low. The value returns to B'000 at
the end of a data transfer, including the acknowledge
bit. These bits are cleared by a power-on reset, in deep
standby mode, software standby mode, or module
standby mode. These bits are also cleared by setting
the IICRST bit of ICCR2 to 1. With the clocked
synchronous serial format, these bits should not be
modified.
I²C Bus Format Clocked Synchronous Serial Format
000: 9 bits
000: 8 bits
001: 2 bits
001: 1 bit
010: 3 bits
010: 2 bits
011: 4 bits
011: 3 bits
100: 5 bits
100: 4 bits
101: 6 bits
101: 5 bits
110: 7 bits
110: 6 bits
111: 8 bits
111: 7 bits
Rev. 2.00 Sep. 07, 2007 Page 739 of 1312
REJ09B0320-0200