SH7261 Datasheet, PDF (90/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.4.7 System Control Instructions
Table 2.16 System Control Instructions
Instruction
CLRT
CLRMAC
LDBANK @Rm,R0
LDC
Rm,SR
LDC
Rm,TBR
LDC
Rm,GBR
LDC
Rm,VBR
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDS
Rm,MACH
LDS
Rm,MACL
LDS
Rm,PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
NOP
RESBANK
RTE
SETT
SLEEP
STBANK R0,@Rn
Instruction Code
0000000000001000
0000000000101000
0100mmmm11100101
0100mmmm00001110
0100mmmm01001010
0100mmmm00011110
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000000000001001
0000000001011011
0000000000101011
0000000000011000
0000000000011011
0100nnnn11100001
Operation
Execu-
tion
Cycles
Compatibility
SH2,
T Bit SH2E SH4 SH-2A
0→T
1
0
Yes Yes Yes
0 → MACH,MACL
1
 Yes Yes Yes
(Specified register bank entry) 6

Yes
→ R0
Rm → SR
3
LSB Yes Yes Yes
Rm → TBR
1

Yes
Rm → GBR
1
 Yes Yes Yes
Rm → VBR
1
 Yes Yes Yes
(Rm) → SR, Rm + 4 → Rm 5
LSB Yes Yes Yes
(Rm) → GBR, Rm + 4 → Rm 1
 Yes Yes Yes
(Rm) → VBR, Rm + 4 → Rm 1
 Yes Yes Yes
Rm → MACH
1
 Yes Yes Yes
Rm → MACL
1
 Yes Yes Yes
Rm → PR
1
 Yes Yes Yes
(Rm) → MACH, Rm + 4 → Rm 1
 Yes Yes Yes
(Rm) → MACL, Rm + 4 → Rm 1
 Yes Yes Yes
(Rm) → PR, Rm + 4 → Rm 1
 Yes Yes Yes
No operation
1
 Yes Yes Yes
Bank → R0 to R14, GBR,
9*

Yes
MACH, MACL, PR
Delayed branch,
stack area → PC/SR
6
 Yes Yes Yes
1→T
1
1
Yes Yes Yes
Sleep
5
 Yes Yes Yes
R0 →
7

Yes
(specified register bank entry)
Rev. 2.00 Sep. 07, 2007 Page 58 of 1312
REJ09B0320-0200