SH7261 Datasheet, PDF (949/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.3.17 IEBus Transmit Interrupt Enable Register (IEIET)
IEIET enables/disables interrupts for sources such as transmit start, transmit normal completion,
and transmit error completion in IETSR.
IEIET is initialized by a power-on reset or in deep standby.
Bit: 7
6
5
4
3
2
1
0
—
TXSE TXFE
—
TX TXE TX TXE
EALE TTMEE EROE ACKE
Initial value: 0
0
0
0
0
0
0
0
R/W: R R/W R/W R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
TXSE
0
R/W Transmit Start Interrupt Enable
Enables/disables a transmit start (TXS) interrupt.
0: Disables a transmit start (TXS) interrupt
1: Enables a transmit start (TXS) interrupt
5
TXFE
0
R/W Transmit Normal Completion Interrupt Enable
Enables/disables a transmit normal completion (TXF)
interrupt.
0: Disables a transmit normal completion (TXF)
interrupt
1: Enables a transmit normal completion (TXF) interrupt
4

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
3
TXEALE 0
R/W Arbitration Loss Interrupt Enable
Enables/disables an arbitration loss (TXEAL) interrupt.
0: Disables an arbitration loss (TXEAL) interrupt
1: Enables an arbitration loss (TXEAL) interrupt
Rev. 2.00 Sep. 07, 2007 Page 917 of 1312
REJ09B0320-0200